The design: it looks so simple ...
This is it, the circuit shown is what will be created - it actually is the output of the RTL schematics viewer of Quartus.
A simple edge triggered latch with an output that is depending on both latched and non-latched input data.
The output C will only be high from the time when input A changes to the next rising clock edge as can be seen from the timing diagram.
The clock signal CLK is driven with a 100 MHz signal. Output B follows A at every clock edge and C is only high from the time that A changes until the next rising clock edge.
All this is created with a a few lines of VHDL code:
entity all_mine is (1)
clk : IN std_logic;
a : IN std_logic;
b : OUT std_logic;
c : OUT std_logic
architecture structure of all_mine is (2)
signal a_latched : std_logic;
b <= a_latched; (3)
c <= a xor a_latched;
latch_a : process (clk) (4)
if rising_edge(clk) then
a_latched <= a;
- Defined the entity all_mine by specifying a port containing all input and output signals.
- This is where the implementation of the components starts.
- The assignment of the output signals. Remember that this all happens in parallel.
- This defines the process for the latch. All statements within the process will be executed in sequential order.
Assigning a value to a_latched will only occur only occurs after a rising edge on the clock.